Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling.pdfseeders: 27
leechers: 8
Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling.pdf (Size: 2.59 MB)
DescriptionSource-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling.pdf  English | ISBN: 1461494044 | 2014 | 160 pages | PDF | 3 MB This book describes novel methods for network-on-chip NoC design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations.   Sharing Widget |